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CYF0018V, CYF0036V CYF0072V
18/36/72 Mbit Programmable FIFOs
18/36/72/144 Mbit Programmable FIFOs
Features
Functional Description
The Cypress programmable FIFO family offers the industry's highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs. This makes it an ideal memory choice for a wide range of applications including multiprocessor interfaces, video and image processing, networking and telecommunications, high-speed data acquisition, or any system that needs buffering at very high speeds across different domains. As implied by the name, the functionality of the FIFO is such that the data is read out of the read port in the same sequence in which it was written into the write port. The data is sequentially written into the FIFO from the write port. If the writes and inputs are enabled, the data on the write port gets written into the device at the rising edge of the write clock. Enabling the reads and outputs fetches data on the read port at every rising edge of the read clock. Both reads and writes can occur simultaneously at different speeds provided the ratio between read and write clock is in the range of 0.5 to 2. Appropriate flags are set whenever the FIFO is empty, full, half-full, almost-full, or almost-empty. The device also supports mark and retransmit of data, and a flow-through mailbox register. All product features and specs are common to all densities ( CYF0072V, CYF0036V, and CYF0018V) unless otherwise specified. All descriptions are given assuming the device is CYF0072V operated in x36 mode. They hold good for other densities (CYF0036V, and CYF0018V) and all port sizes x9, x12, x16, x18, x20, x24 and x32 unless otherwise specified. the only difference will be in the input and output bus width. Table 1 shows the part of bus with valid data from D[35:0] and Q[35:0] in x9, x12, x16, x18, x20, x24, x32 and x36 modes.
Memory organization Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36 Up to 133-MHz clock operation Unidirectional operation Independent read and write ports Supports simultaneous read and write operations Reads and writes operate on independent clocks up to a maximum ratio of two enabling data buffering across clock domains Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards. Input and output enable control for write mask and read skip operations Mark and retransmit: resets read pointer to user marked position Empty, full, half-full, and programmable almost-empty and almost-full status flags with preselected offsets Flow-through mailbox register to send data from input to output port, bypassing the FIFO sequence Configure programmable flags and registers through serial or parallel modes Separate serial clock (SCLK) input for serial programming Master reset to clear entire FIFO Partial reset to clear data but retain programmable settings Joint test action group (JTAG) port provided for boundary scan function Industrial temperature range: -40 C to +85 C

Cypress Semiconductor Corporation Document Number: 001-53687 Rev. *H
*
198 Champion Court
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San Jose, CA 95134-1709 * 408-943-2600 Revised March 31, 2011
CYF0018V, CYF0036V CYF0072V
Logic Block Diagram
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Contents
Pin Definitions ......................................................... 5 Architecture ............................................................. 7 Reset Logic......................................................... 7 Flag Operation.................................................... 7 Full Flag.............................................................. 7 Half-Full Flag ...................................................... 7 Empty Flag ......................................................... 7 Programmable Almost-Empty and Almost-Full Flags................................................ 7 Retransmit from Mark Operation ........................ 7 Flow-through Mailbox Register........................... 7 Selecting Word Sizes ......................................... 8 Power Up.................................................................. 8 Write Mask and Read Skip Operation ................ 8 Programming Flag Offsets and Configuration Registers ...................................... 8 Width Expansion Configuration ........................ 10 Memory Organization for Different Port Sizes .. 11 Read/Write Clock Requirements ...................... 11 JTAG Operation................................................ 12 Maximum Ratings ................................................. Operating Range ................................................... Switching Characteristics .................................... Switching Waveforms........................................... Ordering Information ............................................ Ordering Code Definition.................................. Package Diagram .................................................. Acronyms............................................................... Document Conventions........................................ Units of Measure .............................................. Document History Page........................................ Sales, Solutions, and Legal Information............. Worldwide Sales and Design Support.............. Products ........................................................... PSoC Solutions ................................................ 13 13 15 16 24 24 25 26 26 26 27 29 29 29 29
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G
Pin Diagram for CYF 0 XXX V
Figure 1. 209-Ball FBGA (Top View) 1 A B C D E F G H J K L M N P R T U V W FF EF D4 D6 D8 D10 D12 D14 D16 DNU D18 D20 D22 D24 D26 D28 DVal PAF TDO 2 D0 D2 D5 D7 D9 D11 D13 D15 D17 DNU D19 D21 D23 D25 D27 D29 DNU PAE HF 3 D1 D3 WEN VSS VCC2 VSS VCC2 VSS VCC2 WCLK VCC2 VSS VCC2 VSS VCC2 VSS D30 D32 D34 4 DNU DNU DNU VCC1 VCC2 VSS VCC2 VSS VCC2 DNU VCC2 VSS VCC2 VSS VCC2 VCC1 D31 D33 D35 5 PORTSZ0 DNU VCC1 DNU VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VCC1 PRS DNU TDI 6 PORTSZ1 PORTSZ2 DNU LD VCCIO DNU VCC1 VCC1 VCC1 IE VCC1 VCC1 VCC1 SPI_SEN VCCIO SPI_SI DNU MRS TRST 7 DNU DNU VCC1 DNU VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VSS VCCIO VCC1 SPI_SCLK MB TMS 8 DNU DNU DNU VCC1 VCC2 VSS VCC2 VSS VCC2 DNU VCC2 VSS VCC2 VSS VCC2 VCC1 Vref DNU TCK 9 RT REN RCLK Vss VCC2 VSS VCC2 VSS VCC2 VCCIO VCC2 VSS VCC2 VSS VCC2 VSS OE MARK Vref 10 Q0 Q2 Q4 Q6 Q8 Q10 Q12 Q14 Q16 VCCIO Q18 Q20 Q22 Q24 Q26 Q28 Q30 Q32 Q34 11 Q1 Q3 Q5 Q7 Q9 Q11 Q13 Q15 Q17 VCCIO Q19 Q21 Q23 Q25 Q27 Q29 Q31 Q33 Q35
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Pin Definitions
Pin Name D[35:0] Q[35:0] WEN REN IE I/O Input Output Input Input Input Data inputs: Data inputs for a 36-bit bus Data outputs: Data outputs for a 36-bit bus Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers. Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers. Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This is used for 'write masking' or incrementing the write pointer without writing into a location. Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO's outputs are in High Z (high impedance) state. Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and into the configuration registers if LD is low. Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is high and from the configuration registers if LD is low. Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK. Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. It is synchronized to RCLK. Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset value programmed into the FIFO. It is synchronized to WCLK. Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Master reset: MRS initializes the internal read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the configuration registers are all set to default values and flags are reset. Partial reset: PRS initializes the internal read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the configuration register settings are all retained and flags are reset. Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset registers if SPI_SEN is enabled. Serial input: Serial input data in SPI mode. Serial enable: Enables serial loading of programmable flag offsets and configuration registers. Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any subsequent retransmit operation resets the read pointer to this position. Mailbox: When asserted the reads and writes happen to flow-through mailbox register. Test clock (TCK) Pin for JTAG Reset pin for JTAG Test mode select (TMS) pin for JTAG Test data in (TDI) pin for JTAG Test data out (TDO) for JTAG Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK. Pin Description
OE WCLK RCLK EF FF PAE PAF LD RT
Input Input Input Output Output Output Output Input Input
MRS
Input
PRS SPI_SCLK SPI_SI SPI_SEN MARK MB TCK TRST TMS TDI TDO HF
Input Input Input Input Input Input Input Input Input Input Output Output
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Pin Definitions (continued)
Pin Name DVal PORTSZ [2:0] VCC1 VCC2 VCCIO Vref VSS DNU I/O Output Input Power Supply Power Supply Power Supply Pin Description Data valid: Active low data valid signal to indicate valid data on Q[35:0] Port word size select: Port word width select pins (common for read and write ports) Core voltage supply 1: 1.8V supply voltage Core voltage supply 2: 1.5V supply voltage Supply for I/Os
Input Reference voltage: Reference voltage (regardless of I/O standard used) Reference Ground - Ground Do not use: These pins need to be left floating
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Architecture
The CYF0072V, CYF0036V, and CYF0018V are of memory arrays of 72 Mbit, 36 Mbit, and 18 Mbit respectively. The memory organization is user configurable and word sizes can be selected as x9, x12, x16, x18, x20, x24, x32, or x36. The logic blocks to implement FIFO functionality and the associated features are built around these memory arrays. The input and output data buses have a maximium width of 36 bits. The input data bus goes to an input register and the data flow from the input register to the memory is controlled by the write logic block. The inputs to the write logic block are WCLK, WEN and IE. When the writes are enabled through WEN and if the inputs are enabled by IE, then the data on the input bus is written into the memory array at the rising edge of WCLK. This also increments the write pointer. Enabling writes but disabling the data input pins through IE only increments the write pointer without doing any writes or altering the contents of the location. Similarly, the output register is connected to the data output bus. Transfer of contents from the memory to the output register is controlled by the read control logic. The inputs to the read control logic include RCLK, REN, OE, RT and MARK. When reads are enabled by REN and outputs are enabled through OE, the data from the memory pointed by the read pointer is transferred to the output data bus at the rising edge of RCLK along with active low DVal. If the outputs are disabled but the reads enabled, the outputs are in high impedance state, but internally the read pointer is incremented. During write operation, the number of writes performed is always a even number (i.e., minimum write burst length is two and number of writes always a multiple of two). Whereas during read operation, the number of reads performed can be even or odd (i.e., minimum read burst length is one). The MARK signal is used to `mark' the location from which data is retransmitted when requested. have to be read back in order for full flag to get de-asserted.The minimum number of reads required to de-assert full-flag is two and the maximum number of reads required to de-assert full flag is six.
Half-Full Flag
The Half-Full (HF) flag goes LOW when half of the memory array is written. The assertion of HF is synchronized to WCLK. The assertion and de-assertion of Half-Full flag with associated latencies is explained in Table 12
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, that is, it is exclusively updated by each rising edge of RCLK. The assertion and de-assertion of empty flag with associated latencies is explained in Table 12
Programmable Almost-Empty and Almost-Full Flags
The CYF0072V includes programmable Almost-Empty and Almost-Full flags. Each flag is programmed (see Programming Flag Offsets and Configuration Registers on page 8) a specific distance from the corresponding boundary flags (Empty or Full). (offset can range from 16 to 1024) When the FIFO contains the number of words (or fewer) for which the flags are programmed, the PAF or PAE is asserted, signifying that the FIFO is either almost-full or almost-empty. The PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. The assertion and de-assertion of empty flag with associated latencies is explained in Table 12
Retransmit from Mark Operation
The retransmit feature is useful for transferring packets of data repeatedly. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit feature is used when the number of writes after MARK is equal to or less than the depth of the FIFO and at least one word has been read since the last reset cycle. A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO that is marked by the user (using the MARK pin). With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to FIFO after activation of RT are also transmitted. The full depth of the FIFO can be repeatedly retransmitted. To mark a location, the Mark pin is asserted when reading that particular location.
Reset Logic
The FIFO can be reset in two ways: Master Reset (MRS) and Partial Reset (PRS). The MRS initializes the read and write pointers to zero and sets the output register to all zeroes. It also resets the configuration registers to their default values. The word size is configured through pins; values of the three PORTSZ pins are latched during MRS. A Master Reset is required after power-up before accessing the FIFO. The PRS resets only the read and write pointer to the first location and does not affect the programmed configuration registers.
Flag Operation
This device provides five flag pins to indicate the condition of the FIFO contents.
Full Flag
The Full Flag (FF) goes LOW when the device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, that is, it is exclusively updated by each rising edge of WCLK. The worst case assertion latency for Full Flag is four. As the user cannot know that the FIFO is full for four clock cycles, it is possible that user continues writing data during this time. In this case, the four data word written will be stored to prevent data loss and these words Document Number: 001-53687 Rev. *H
Flow-through Mailbox Register
This feature transfers data from input to output directly by bypassing the FIFO sequence. When MB signal is asserted the data present in D[35:0] will be available at Q[35:0] after two WCLK cycles. Normal read and write operations are not allowed during flow-through mailbox operation. Before starting Flow-through mailbox operation FIFO read should be completed to make data valid DVal high in order to avoid data loss from FIFO. The width of flow-through mailbox register always corresponds to port size. Page 7 of 29
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Selecting Word Sizes
The word sizes are configured based on the logic levels on the PORTSZ pins during the master reset (MRS) cycle only (latched on low to high edge). The port size cannot be changed during normal mode of operation and these pins are ignored. Table 1. explains the pins of D[35:0] and Q[35:0] that will have valid data in modes where the word size is less than x36. If word size is less than x36, the unused output pins are tri-stated by the device and unused input pins will be ignored by the internal logic. The pins with valid data input D[N:0] and output Q[N:0] is given in Table 1. a read operation is performed, the DVal signal goes low along with output data. This helps user to capture the data without keeping track of REN to data output latency. This signal also helps when write and read operations are performed continuously at different frequencies by indicating when valid data is available at the output port Q[35:0].
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and Vref attain minimum stable voltage required as given in Recommended DC Operating Conditions on page 13. The device can be accessed tPU time after these supplies attain the minimum required level (see Switching Characteristics on page 15). There is no particular power sequencing required for the device.
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal, synchronized to RCLK and is provided for easy capture of output data to the user. When Table 1. Word Size Selection PORTSZ[2:0] 000 001 010 011 100 101 110 111 Word Size x9 x12 x16 x18 x20 x24 x32 x36
Active Input Data Pins D[X:0] Active Output Data Pins Q[X:0] D[8:0] D[11:0] D[15:0] D[17:0] D[19:0] D[23:0] D[31:0] D[35:0] Q[8:0] Q[11:0] Q[15:0] Q[17:0] Q[19:0] Q[23:0] Q[31:0] Q[35:0]
Write Mask and Read Skip Operation
As mentioned in Architecture on page 7, enabling writes but disabling the inputs (IE HIGH) increments the write pointer without doing any write operations or altering the contents of the location. This feature is called Write Mask and allows user to move the write pointer without actually writing to the locations. This "write masking" ability is useful in some video applications such as Picture In Picture (PIP). Similarly, during a read operation, if the outputs are disabled by having the OE high, the read data does not appear on the output bus; however, the read pointer is incremented.
pin. A low on the SPI_SEN selects the serial method for writing into the registers. For serial programming, there is a separate SCLK and a Serial Input (SI). In parallel mode, a low on the load (LD) pin causes the write and read operation to these registers. The write and read operation happens from the first location (0x1) to the last location (0xA) in a sequence. If LD is high, the writes occur to the FIFO. In addition to loading register values into the FIFO, it is also possible to read the current register values. Register values can be read through the parallel output port regardless of the programming mode selected (serial or parallel). Register values cannot be read serially. The registers may be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming is selected. See Table 3 on page 9 and Table 4 on page 10 for access to configuration registers in serial and parallel modes. In parallel mode, the read and write operations loop back when the maximum address location of the configuration registers is reached. Simultaneous read and write operations should be avoided on the configuration registers. Any change in configuration registers will take effect after eight write clock cycles(WCLK) cycles.
Programming Flag Offsets and Configuration Registers
The CYF0072V has ten 8-bit user configurable registers. These registers contain the almost-full offset (M) and almost-empty (N) values which decide when the PAF and PAE flags are asserted. These registers can be programmed into the FIFO in one of two ways: using either the serial or parallel loading method. The loading method is selected using the SPI_SEN (Serial Enable)
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Table 2. Configuration Registers ADDR 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Configuration Register Reserved Reserved Reserved Default 0x00 0x00 0x00 Bit [7] X X X D7 X X D7 X X Bit [6] X X X D6 X X D6 X X X Bit [5] X X X D5 X X D5 X X X Bit [4] X X X D4 X X D4 X X X Bit [3] X X X D3 X X D3 X X X Bit [2] X X X D2 X X D2 X X X Bit [1] X X X D1 D9 X D1 D9 X X Bit [0] X X X D0 D8 X D0 D8 X X
Almost-Empty Flag generation 0x7F address - (LSB) (N) Almost-Empty Flag generation 0x00 address - (MSB) (N) Reserved Almost-Full Flag generation address - (LSB) (M) Almost-Full Flag generation address - (MSB) (M) Reserved Fast CLK Bit Register 0x00 0x7F 0x00 0x00
1XXXXXXXb Fast CLK bit
Table 3. Writing and Reading Configuration Registers in Parallel Mode SPI_SEN 1 LD 0 WEN 0 REN 1 WCLK First rising edge because both LD and REN are low Second rising edge Third rising edge Fourth rising edge Tenth rising edge Eleventh rising edge X RCLK X SPI_SCLK X Operation Parallel write to first register
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 0
X X X X X X X X First rising edge since both LD and REN are low Second rising edge Third rising edge Fourth rising edge Tenth rising edge
X X X X X X X X X
Parallel write to second register Parallel write to third register Parallel write to fourth register Parallel write to tenth register Parallel write to first register (roll back) Parallel read from first register
1 1 1 1 1 1 1
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
X X X X X X X
X X X X X X X
Parallel read from second register Parallel read from third register Parallel read from fourth register Parallel read from tenth register
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Table 3. Writing and Reading Configuration Registers in Parallel Mode (continued) SPI_SEN 1 1 X X 0 LD 0 X 1 1 0 WEN 1 1 0 X X REN 0 1 X 0 1 WCLK X X Rising edge X X RCLK Eleventh rising edge X X Rising edge X SPI_SCLK X X X X X Operation Parallel read from first register (roll back) No operation Write to FIFO memory Read from FIFO memory Illegal operation
Table 4. Writing into Configuration Registers in Serial Mode SPI_SEN 0 LD 1 WEN X REN X WCLK X RCLK X SCLK Operation
Rising edge Each rising of the SCLK clocks in one bit from the SI (Serial In). Any of the 10 registers can be addressed and written to, following the SPI protocol. X X X Parallel write to FIFO memory. Parallel read from FIFO memory. This corresponds to parallel mode (refer to Table 3).
X X 1
1 1 0
0 X 1
X 0 1
Rising edge X X
X Rising edge X
Figure 2. Serial WRITE to Configuration Register
Width Expansion Configuration
The width of CYFX072V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is "staggered" by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 on page 11 demonstrates an example of 72 bit-word width by using two 36-bit word CYFX072Vs.
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Figure 3. Using Two CYFX072V for Width Expansion
DATAIN (D) 72
36
36
WRITE CLOCK (WCLK) WRITE ENABLE (WEN)
CYFX072V
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE(OE)
CYFX072V
PAE HF FF FF
PAF EF
EF
36
FF
EF
36
DATAOUT (Q)
72
Memory Organization for Different Port Sizes
The 72-Mbit memory has different organization for different port sizes. Table 5 shows the depth of the FIFO for all port sizes. Note that for all port sizes, four to eight locations are not available for writing the data and are used to safeguard against false synchronization of empty and full flags. Table 5. Word Size Selection
PORTSZ[2:0] 000 001 010 011 100 101 110 111 Word Size x9 x12 x16 x18 x20 x24 x32 x36 FIFO Depth 8 Meg 4 Meg 4 Meg 4 Meg 2 Meg 2 Meg 2 Meg 2 Meg Memory Size 72 Mbit 48 Mbit 64 Mbit 72 Mbit 40 Mbit 48 Mbit 64 Mbit 72 Mbit
Read/Write Clock Requirements
The read and write clocks must satisfy the following requirements:

Both read (RCLK) and write (WCLK) clocks should be free-running. The clock frequency for both clocks should be between the minimum and maximum range given in Table 10 on page 13. The WCLK to RCLK ratio should be in the range of 0.5 to 2.
For proper FIFO operation, the device must determine which of the input clocks - RCLK or WCLK - is faster. This is evaluated by using counters after the MRS cycle. The device uses two 10-bit counters inside (one running on RCLK and other on WCLK), which count 1,024 cycles of read and write clock after MRS. The clock of the counter which reaches its terminal count first is used as master clock inside the FIFO. When there is change in the relative frequency of RCLK and WCLK during normal operation of FIFO, user can specify it by using "Fast CLK bit" in the configuration register (0xA). "1" - indicates freq (WCLK) > freq (RCLK) "0" - indicates freq (WCLK) < freq (RCLK) The result of counter evaluated frequency is available in this register bit. User can override the counter evaluated frequency for faster clock by changing this bit. Whenever there is a change in this bit value, user must wait tPLL time before issuing the next read or write to FIFO.
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JTAG Operation
CYFX072V has two devices connected internally in a JTAG chain as shown in Figure 4 Figure 4. Device Connection in a JTAG Chain
TRST TM S TCK TM S TCK device1 TDI TDI TDO TDO TM S TRST TCK device2 TDI TDO
Table 6 shows the IR register length and device ID Table 6. JTAG IDCODES Device-1 Device-2 IR Register Length 3 8 Device ID (HEX) "Ignore" 1E3261CF Bypass Register Length 1 1
Table 7. JTAG Instructions for Device-1 Device-1 BYPASS Table 8. JTAG Instructions for Device-2 Device-2 EXTEST HIGHZ SAMPLE/PRELOAD BYPASS IDCODE Opcode (HEX) 00 07 01 FF 0F Opcode (Binary) 111
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature (without bias) ............ -65 C to +150 C Ambient temperature with power applied -55 C to +125 C I/O port supply voltage (VCCIO) ............................-0.3 V to 3.7 V Voltage applied to I/O pins ...........................-0.3 V to 3.75 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015)
Core supply voltage 1 (VCC1) to ground potential.................................................-0.3 V to 2.5 V Core supply voltage 2 (VCC2) to ground potential...............................................-0.3 V to 1.65 V Latch up current .................................................... >100mA Table 9. Recommended DC Operating Conditions Parameter VCC1 VCC2 Vref VCCIO Description Core supply voltage 1 Core supply voltage 2
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C
Min 1.70 1.425 0.7 3.00 1.70
Typ 1.80 1.5 0.75 3.30 1.8
Max 1.90 1.575 0.8 3.60 1.90
Unit V V V V V
Reference voltage (irrespective of I/O standard used) I/O supply voltage, read and write LVCMOS33 banks. LVCMOS18
Table 10. Electrical Characteristics Parameter Icc Description Active current Conditions VCC1=VCC1MAX, VCC2=VCC2MAX, All I/O switching, 133 MHz) VCCIO = VCCIOMAX (All outputs disabled) II IOZ CP CPIO Input pin leakage current VIN = VCCIOmax to 0 V I/O pin leakage current Capacitance for TMS and TCK VO = VCCIOmax to 0 V - Min - - Typ - - Max 300 600 Unit mA mA
- -15 -15 - -
- - - - -
100 15 15 16 8
mA A A pF pF
Capacitance for all other - pins except TMS and TCK
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Table 11. I/O Characteristics (Over the operating range) I/O standard LVCMOS33 LVCMOS18 Nominal I/O supply voltage 3.3 V 1.8 V Input Voltage (V) VIL(max) 0.80 30% VCCIO VIH(min) 2.20 65% VCCIO Output voltage (V) VOL(max) 0.45 0.45 VOH(min) 2.40 VCCIO - 0.45 Output Current (mA) IOL(max) 24 16 IOH(max) 24 16
Table 12. Latency Table Latency Parameter LFF_ASSERT LEF_ASSERT LPRS_TO_ACTIVE LMAILBOX LREN_TO_DATA LREN_TO_CONFIG LWEN_TO_PAE_HI LWEN_TO_PAF_LO LREN_TO_PAE_LO LREN_TO_PAF_HI LFF_DEASSERT LRT_TO_REN LRT_TO_DATA LIN LEF_DEASSERT Number of cycles Min=0 Max=4 0 1 2 4 4 5 5 7 7 8 9 Min=19 Max=21 Min=25 Max=26 Min=23 Max=24 Last data write to FF going low Last data read to EF going low PRS to normal operation Latency from write port to read port when MB = 1 (wrt WCLK) Latency when REN is asserted low to first data output from FIFO Latency when REN is asserted along with LD to first data read from configuration registers Write to PAE going low Write to PAF going low Read to PAE going high Read to PAF going high Read to FF going high RT fifth cycle to REN going low for read RT fifth cycle to valid data on Q[35:0] Initial latency for data read after FIFO goes empty during simultaneous read/write Write to EF going high Detail
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Switching Characteristics
Parameter tPU tS tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tENS_SI tENH_SI tRATE_SPI tRS tPZS tPZH tRSF tPRT tOLZ tOE tOHZ tWFF tREF tPAF tPAE tHF tPLL tRATE_JTAG tS_JTAG tH_JTAG tCO_JTAG Description Power-up time after all supplies reach minimum value Clock cycle frequency Clock cycle frequency Data access time Clock cycle time Clock high time Clock low time Data setup time Data hold time Enable setup time Enable hold time Setup time for SPI_SI and SPI_SEN pins Hold time for SPI_SI and SPI_SEN pins Frequency of SCLK Reset pulse width Port size select to MRS seup time MRS to port size select hold time Reset to flag output time Retransmit pulse width Output enable to output in Low Z Output enable to output valid Output enable to output in High Z Write clock to FF Read clock to EF Clock to PAF flag Clock to PAE flag Clock to HF flag Time required to synchronize PLL JTAG TCK cycle time Setup time for JTAG TMS,TDI Hold time for JTAG TMS,TDI JTAG TCK low to TDO valid 7.5 3.375 3.375 3 3 3 3 5 5 - 100 25 25 - 5 4 - - - - - - - - 100 5 5 - 3.3 V LVCMOS 1.8 V LVCMOS -133 Min - 24 24 Max 2 133 133 10 41.67 - - - - - - - - 25 - - - 50 - 15 15 15 8.5 8.5 17 17 17 1024 - - - 10 Unit ms MHz MHz ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns RCLK cycles ns ns ns ns ns ns ns ns cycles ns ns ns ns
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Switching Waveforms
Figure 5. Write Cycle Timing
tCLK
tCLKH WCLK
tCLKL
tDS D[35:0] tENS
tDH
tENH
NO OPERATION
WEN, IE
Figure 6. Read Cycle Timing
tCLK
RCLK tENS REN tENH
NO OPERATION
LREN_TO_DATA
tA Q[35:0] tOLZ OE
VALID DATA
tOHZ
DVal
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Switching Waveforms (continued)
Figure 7. Reset Timing
MRS
tRS
tRSF EF,PAE tRSF FF,PAF, HF tRSF Q[35:0] - OE=1 OE=0
Figure 8. MRS to PORTSZ[2:0]
WCLK/RCLK tPZS tPZH
MRS
PORTSZ[2:0]
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Switching Waveforms (continued)
Figure 9. Empty Flag Timing
RCLK tREF EF REN OE
Q[35:0]
Q(Last)-3
Q(Last)-2
Q(Last)-1
Q(Last)
Invalid Data
DVal
Figure 10. Full Flag Timing
WCLK tDS D[35:0] D0 (written) D1 (written) D2 (written) D3 (not written) tWFF FF D4 (not written)
WEN
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Figure 11. Initial Data Latencyn
1
WCLK /RCLK D[35:0] D0
2
D1
D2
tA
D3
D4
WEN/REN OE Q[35:0] DVal
Q0
Q1
LIN (initial latency)
Figure 12. Flow-through Mailbox Operation
WCLK
1
2
3
D[35:0]
DO
D1
D2
D3
D4
REN / WEN
L MAILBOX
MB Q[35:0]
QO Q1 Q2 Q3 Q4
DVal
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Figure 13. Configuration Register Write
WCLK tENS WEN / IE
LD tDS D[35:0]
config-reg 0 config-reg 1
tDH
config-reg 2 config-reg 3 config-reg 4 config-reg 5
Figure 14. Configuration Register Read
WCLK /RCLK REN LREN_TO_CONFIG LD
tA
Q[35:0]
Reg - 1
Figure 15. Empty Flag Deassertion
WCLK
WEN / IE
D[35:0]
D0
D1
L EF_DEASSERT EF tREF RCLK
REN
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Figure 16. Empty Flag Assertion
RCLK
1
2
3
4
5
REN
tA
Q[35:0]
Q LAST
DVal L REN_TO_DATA EF tREF
Figure 17. Full Flag Assertion
WCLK
WEN / IE
D[35:0]
D 0
D 1
D x
D LAST-1
D LAST
NOT WRITTEN
NOT WRITTEN
FF
Figure 18. Full Flag Deassertion
WCLK
WEN / IE
D[35:0] LAST-5
D
D LAST-4
D LAST-3
D LAST-2
D LAST-1
D LAST
L FF_DEASSERT
FF
1 2 3 7 8
RCLK
REN
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Figure 19. PAE Assertion and Deassertion
WCLK
WEN / IE
WEN for OFFSET +1 LOCATION
RCLK
REN
L WEN_TO_PAE_HI
1 READ
L REN_TO_PAE_LO
PAE
tPAE
tPAE
Figure 20. PAF Assertion and Deassertion
WCLK
WEN / IE
FULL - (OFFSET +1) WRITE
RCLK
REN L WEN_TO_PAF_LO PAF
tPAF 1 READ
L REN_TO_PAF_HI
tPAF
Figure 21. HF Assertion and Deassertion
WCLK
WEN / IE
FULL / 2 WRITE
RCLK
REN
L WEN_TO_PAF_LO
1 READ
L REN_TO_PAF_HI
HF tHF tHF
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Figure 22. Mark
RCLK tENS REN tENH MARK
Q[35:0] Q (N-2)
Q (N-1)
Q (N)
Q (N+1)
Q (N+2)
Q (N+3)
Q (N+4)
Q (N+5)
Q (N+6)
DVal
DATA MARKED
Figure 23. Retransmit
RCLK
REN
tPRT
LRT_TO_REN LRT_TO_DATA
RT_FL Q[35:0]
Q (N) Q (N+1)
RETRANSMIT FROM DATA MARKED
DVal
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Ordering Information
Speed (MHz) 133 Ordering Code CYF0018V33L-133BGXI CYF0036V33L-133BGXI CYF0072V33L-133BGXI CYF0018V18L-133BGXI CYF0036V18L-133BGXI CYF0072V18L-133BGXI Package Diagram Package Type Operating Range Industrial 51-85167 209-ball fine-pitch ball grid array (FPBGA) (14 x 22 x 1.76 mm)
Ordering Code Definition
CY F X XXX VXX X - XXX BGXI
Speed: 133 MHz
I/O Standard: L = LVCMOS I/O Voltage: 18 = 1.8 V 33 = 3.3 V Density: 018 = 18M 036 = 36M 072 = 72M
0 - single-queue
FIFO Cypress
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Package Diagram
Figure 24. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167 *A
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Acronyms
Acronym FF FIFO HF HSTL IE I/O FPBGA JTAG LVCMOS MB MRS OE PAF PAE PRS RCLK REN RCLK SCLK TDI TDO TCK TMS WCLK WEN Full flag First in first out Half full High-speed transceiver logic Input enable Input/output fine-pitch ball grid array Joint test action group Low voltage complementary metal oxide semiconductor Mailbox Master reset Output enable Programmable almost-full Programmable almost-empty Partial reset Read clock Read enable Read clock Serial clock Test data in Test data out Test clock Test mode select Write clock Write enable Description
Document Conventions
Units of Measure
Symbol C A mA ms MHz ns pF V W Unit of Measure degrees Celsius microampere milliampere millisecond megahertz nanosecond ohm pico Farad volt watt
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Document History Page
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 Mbit Programmable FIFOs Document Number: 001-53687 Rev. ** *A *B ECN No. 2711566 2725088 2839536 Orig. of Change VKN/PYRS NXR NXR Submission Date 05/27/09 New data sheet Description of Change
06/26/2009 Included pinout, AC and DC specs, timing diagrams and package diagram 01/28/2010 Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU, Balls C5, C7, G6, H6, J6, L6, M6, N6, T5, T7 FROM NC to VCC1, Balls K9, K10, K11 From NC to VCCIOR Ball W9 from NC to Vref in pin configuration table Swapped Voltage range of VSS1 and VSS2 Updated ICC spec Removed TSKEW parameter Added Ordering Information table Added Part Numbering Nomenclature. Changed title to CYF0018V/CYF0036V/CYF0072V/CYFX144VXXX, 18/36/72 Mbit Programmable FIFOs. 02/25/2010 Post to external web. 06/28/2010 Changed frequency of operation from 250 MHz to 150 MHz Removed Depth Expansion feature and changed associated pin functionality Removed Independent Port size selectability feature Added Data Valid (DVal) signal feature Updated Logic Block Diagram to reflect above changes. Pinout changes: Balls V5, V8, A7, B7, D7, and C6 renamed DNU Ball U1 changed from RXO to DVal Ball V2 changed from WXO/HF to HF Ball A5, A6, B6 changed from WPORTSZ to PORTSZ Ball A9 changed from RT/FL to RT Renamed pwr as POWER, gnd as GND Added Table 3 Table 6 - LD changed to `1' for serial writes Updated Electrical Characteristics and I/O Characteristics Switching Characteristics Table: Renamed tPC as tPU Min frequency changed from 110MH to 24MHz Changed tCLKH and tCLKL to 3.15 ns Changed All setup and hold times to 3 ns Changed tRSF to 50 ns Removed tRSR Changed All clock-to-flag timing to min=8 ns and max=14 ns TPLL changed to 6 ms Changed all OE-related parameters to 15 ns Scaled ICC for reduced frequency Updated all waveforms Added the following tables: Word Size Selection, JTAG Operation, and Latency Table Added Acronyms. 07/26/2010 Updated Ordering Information 12/03/2010 Added supply-wise current consumption data in Electrical Characteristics. Changed initial latency LIN from 34 to 26 and added initial latency LIN for 110 MHz part in Latency Table. Added 110 MHz part information in JTAG Operation Added details for the 110 MHz part in Switching Characteristics. Added details for the 110 MHz part in Ordering Information. 01/06/2011 Post to external web.
*C *D
2884377 2963225
HKV AJU/HPV
*E *F
2994379 3101023
AJU SIVS
*G
3129722
HKV
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Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 Mbit Programmable FIFOs Document Number: 001-53687 Rev. *H ECN No. 3197271 Orig. of Change SIVS Submission Date Description of Change
03/31/2011 Removed 144 Mbit parts from the data sheet Removed multi-queue information from data sheet Removed 2.5 V and 1.5 V options Removed HSTL I/II I/O standard Added clock ratio requirement between RCLK and WCLK Removed redundant Xs from part number to improve readability Removed tie to GND option on DNU pins in pin description Added information on Flag operations to add clarity Added explanation for flow-through mailbox operation Added details on active pins in various port sizes in Table 1. Added Configuration register write to normal operation latency details. Changed configuration register definitions and default values Changed number of unusable locations to four to eight Added JTAG related operation Added latch-up current parameter in maximum operating conditions. Removed 2.5 V and 1.5 V options from DC operating condition table 6. Removed 110 MHz part details and added Cpio parameter in table 7. Removed 2.5 V and 1.5 V options from Table 8. Added latency parameters in Table 9. changed Vol(max) value of LVCMOS33 in table11 Removed 110 MHz part detail from switching characteristics Added timing waveform to improve clarity. Modified ordering information and definition.
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(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53687 Rev. *H
Revised March 31, 2011
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